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50 ma/500 ma, high efficiency, ultralow power step-down regulator data sheet ADP5301 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2015 analog devices, inc. all rights reserved. technical support www.analog.com features input start-up voltage range: 2.15 v to 6.50 v operates down to 2.00 v voltage ultralow 180 na quiescent current with no load selectable output voltage of 1.2 v to 3.6 v or 0.8 v to 5.0 v 1.5% output accuracy over full temperature range in pwm mode selectable hysteresis mode or pwm operation mode output current up to 50 ma in hysteresis mode up to 500 ma in pwm mode voutok flag monitors the output voltage 100% duty cycle operation mode 2 mhz switching frequency with optional synchronization input from 1.2 mhz to 2.5 mhz qod option uvlo, ocp, and tsd protection 9-ball, 1.65 mm 1.87 mm wlcsp ?40c to +125c junction temperature applications energy (gas and water) metering portable and battery-powered equipment medical applications keep-alive power supplies typical application circuit pwm 13169-001 2.2h sw pgnd fb 10f 10f v out pvin sync/ mode en vid v in = 3.6v ADP5301 (9-ball wlcsp) hys r vid off on voutok vid0: 1.2v vid1: 1.5v vid2: 1.8v vid3: 2.0v vid4: 2.1v vid5: 2.2v vid6: 2.3v vid7: 2.4v vid8: 2.5v vid9: 2.6v vid10: 2.7v vid11: 2.8v vid12: 2.9v vid13: 3.0v vid14: 3.3v vid15: 3.6v agnd figure 1. general description the ADP5301 is a high efficiency, ultralow quiescent current step-down regulator that draws only a 180 na quiescent current to regulate the output at no load. the ADP5301 runs from an input startup voltage range of 2.15 v to 6.50 v, allowing the use of multiple alkaline/nimh, li-ion cells, or other power sources. the output voltage is selectable from 0.8 v to 5.0 v by an external vid resistor and factory fuse. the total solution requires only four tiny external components. the ADP5301 can operate between hysteresis mode and pwm mode via the sync/mode pin. the regulator in hysteresis mode achieves excellent efficiency at a power of less than 1 mw and provides up to 50 ma of output current. the regulator in pwm mode produces a lower output ripple and supplies up to 500 ma of output current. the flexible configuration capability during operation of the device enables very efficient power management to meet both the longest battery life and low system noise requirements. the ADP5301 contains a voutok flag, which monitors the output voltage and runs at a 2 mhz switching frequency in pwm mode. sync/mode can synchronize to an external clock from 1.2 mhz to 2.5 mhz. other key features in the ADP5301 include separate enabling, quick output discharge (qod), and safety features such as overcurrent protection (ocp), thermal shutdown (tsd), and input undervoltage lockout (uvlo). the ADP5301 is available in a 9-ball, 1.65 mm 1.87 mm wlcsp rated for a ?40c to +125c junction temperature range.
ADP5301 data sheet rev. a | page 2 of 21 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical applicat ion circuit ............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 absolute maxim um ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 14 buck regulator operation modes ............................................ 14 oscillator and synchronization ................................................ 14 adjustable and fixed output voltages .................................... 14 undervoltage lockout (uvlo) ............................................... 15 enable/disable ............................................................................ 15 current limit .............................................................................. 15 short - circuit protection ............................................................ 15 soft start ...................................................................................... 15 startup with a pre charged output ........................................... 15 100% duty cycle operation ..................................................... 15 active discharge ......................................................................... 15 voutok function ................................................................... 15 thermal shut down .................................................................... 15 applications information .............................................................. 16 external component selection ................................................ 16 selecting the inductor ................................................................ 16 output capacitor ........................................................................ 16 input capacitor ........................................................................... 17 efficiency ..................................................................................... 17 printed circuit board (pcb) layout recommendations ..... 18 typical application circuits ......................................................... 19 factory programmable options ................................................... 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 12/15 rev. 0 to rev. a changes to ordering guide .......................................................... 21 6 /1 5 rev ision 0 : initial version
data sheet ADP5301 rev. a | page 3 of 21 functional block diagram 13169-002 voutok mode internal feedback resistor divider soft start 90% 87% fb control logic i lim_pwm i lim_hys standby 0.808v ?0.6a(pwm) 0.8v v to i 0a(hys) 0.8v pwm driver pvin pvin sw pgnd fb 1.2v 0.4v sync mode 1.2v 0.4v pvin uvlo band gap bias and housekeeping keep alive block 2.06v 2.00v en sync/ mode driver pvin vid a gnd 2mhz osc slope compensation figure 2.
ADP5301 data sheet rev. a | page 4 of 21 specifications v in = 3.6 v, v out = 2.5 v, t j = ? 40c to + 125c for minimum and maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. table 1 . parameter symbol min typ max unit test conditions/comments input supply voltage range v in 2.15 6.50 v shutdown current i shutdown 18 40 na v en = 0 v, ? 40c t j + 85c 18 130 na v en = 0 v, ? 40c t j + 125c quiescent current operating quiescent current in hysteresis mode i q_hys 180 260 na ? 40c t j + 85c 180 350 na ? 40c t j +1 25c 570 1400 na 100% duty cycle operation, v in = 3.0 v, v out set to 3.3 v operating quiescent current in pwm mode i q_pwm 425 630 a undervoltage lockout uvlo uvlo threshold rising v uvlo_rising 2.0 6 2.14 v falling v uvlo_falling 1.90 2.00 v oscillator circuit switching frequency in pwm mode f sw 1.7 2.0 2.3 mhz fb threshold of frequency fold v osc_fold 0.3 v synchronization threshold sync clock range sync clock 1.2 2.5 mhz sync high level threshold sync high 1.2 v sync low level threshold sync low 0.4 v sync duty cycle range sync duty 100 1/f sw ? 150 ns sync/mode leakage current i sync_leakage 50 150 na v sync/mode = 3.6 v mode transition transition delay from hysteresis mode to pwm mode t hys_to_pwm 20 clock c ycle s sync/mode goes logic high from logic low en pin input voltage threshold high v ih 1.2 v low v il 0.4 v input leakage current i en_leakage 25 na fb pin output options by vid resistor v out _opt 0.8 5.0 v 0.8 v to 5.0 v in various factory option s pwm mode fixed vid code voltage accuracy v fb_pwm_fix ? 0. 6 + 0. 6 % t j = 25c, o utput voltage setting via factory fuse ?1.2 +1.2 % ?40c t j +125 c adjustable vid code voltage accuracy v fb_pwm_adj ?1.5 +1.5 % output voltage setting via vid resistor hysteresis mode fixed vid code threshold accuracy from active mode to standby mode v fb_hys_fix ?0.7 5 +0.7 5 % t j = 25c ?2.5 +2.5 % ?40c t j +125c adjustable vid code threshold accuracy from active mode to standby mode v fb_hys_adj ?3 +3 % ?40c t j +125c hysteresis of threshold accuracy from active mode to standby mode v fb_hys (hys) 1 % feedback bias current i fb 66 95 na output o ption 0, v out = 2.5 v 25 45 na output o ption 1, v out = 1.3 v
data sheet ADP5301 rev. a | page 5 of 21 parameter symbol min typ max unit test conditions/comments sw pin high - side power fet on resistance r ds (on) h 3 24 470 m? pin to pin measurement low - side power fet on resistance r ds (on) l 196 320 m? pin to pin measurement current - limit in pwm mode i lim_pwm 800 1000 1200 ma sync/mode = high peak current in hysteresis mode i lim_hys 265 ma sync/mode = low minimum on time t min_on 40 70 ns voutok pin monitor threshold v outok (rise) 87 90 93 % monitor hysteresis v outok (hys) 3 % monitor rising delay t voutok_rise 40 s monitor falling delay t voutok_fall 10 s leakage current i voutok_leakage 0.1 1 a output low voltage v outok_low 50 80 mv i voutok = 100 a soft start default soft start time t ss 350 s factory trim, 1 bit (350 s and 2800 s) start - up delay t start_delay 2 ms delay from the en pin being pulled high c out discharge switch on resistance r dis 290 ? thermal shutdown threshold t shdn 142 c hysteresis t hys 127 c
ADP5301 data sheet rev. a | page 6 of 21 absolute maximum rat ings table 2 . parameter rating pvin to pgnd ?0.3 v to + 7 v sw to pgnd ? 0. 3 v to pvin + 0.3 v fb to agnd ?0.3 v to + 7 v vid to agnd ?0.3 v to +7 v en to agnd ?0.3 v to +7 v voutok to agnd ?0.3 v to +7 v sync/mode to a gnd ?0.3 v to + 7 v pgnd to agnd ?0.3 v to +0.3 v storage temperate range ?65 c to +150c operational junction temperature range ?40c to +125c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress ra ting only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3 . thermal resistance package type ja unit 9 - ball wlcsp 132 c/w esd caution
data sheet ADP5301 rev. a | page 7 of 21 pin configuration and fu nction descriptions 13169-003 a1 a2 a3 b1 b2 b3 c1 c2 c3 en pgnd pvin agnd voutok sync/ mode vid fb sw ADP5301 figure 3. pin configuration (top view) table 4. pin function descriptions pin no. mnemonic description a1 sw switching node output for the regulator. a2 pvin power input for the regulator. a3 en enable input for the regulator. set this pin to logic low to disable the regulator. b1 pgnd power ground. b2 agnd analog ground. b3 sync/mode synchronization input pin (sync). to synchronize the switching frequency of the device to an external clock, connect this pin to an external clock with a frequency from 1.2 mhz to 2.5 mhz. pwm or hysteresis mode selection pin (mode). when this pin is logic high, the regulator operates in pwm mode. when this pin is logic low, the regulator operates in hysteresis mode. c1 voutok output power-good signal. this open-drain o utput is the power-good signal for the output voltage. c2 fb feedback sensing input for the regulator. c3 vid voltage configuration pin. connect an external resistor (r vid ) from this pin to ground to configure the output voltage of the regulator (see table 5).
ADP5301 data sheet rev. a | page 8 of 21 typical performance characteristics v in = 3.6 v, v out = 2.5 v, l = 2.2 h, c in = c out = 10 f, f sw = 2 mhz, t a = 25c, unless otherwise noted. 13169-004 efficiency (%) load current (ma) 100 90 80 70 60 50 40 30 0.001 0.010 0.100 1.000 10.000 v in = 2.5v v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v figure 4. hysteresis efficiency vs. load current, v out = 1.2 v 13169-005 efficiency (%) load current (ma) 100 90 80 70 60 50 40 0.001 0.010 0.100 1.000 10.000 v in = 2.5v v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v figure 5. hysteresis efficiency vs. load current, v out = 1. 8 v 13169-006 efficiency (%) load current (ma) 100 90 80 70 60 50 0.001 0.010 0.100 1.000 10.000 v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v figure 6. hysteresis efficiency vs. load current, v out = 3.3 v 13169-007 efficiency (%) load current (ma) 100 90 80 70 60 50 40 0.001 0.010 0.100 1.000 10.000 v in = 2.5v v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v figure 7. hysteresis efficiency vs. load current, v out = 1.5 v 13169-008 efficiency (%) load current (ma) 100 90 80 70 60 50 0.001 0.010 0.100 1.000 10.000 v in = 3.6v v in = 3.0v v in = 4.2v v in = 5.0v v in = 6.0v figure 8. hysteresis efficiency vs. load current, v out = 2.5 v 13169-009 efficiency (%) load current (ma) 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 v in = 2.5v v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v figure 9. pwm efficiency vs. load current, v out = 1.2 v
data sheet ADP5301 rev. a | page 9 of 21 13169-010 efficiency (%) load current (ma) 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 v in = 2.5v v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v figure 10 . pwm efficiency vs. load current, v out = 1. 5 v 13169-0 1 1 efficiency (%) load current (ma) 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v figure 11 . pwm efficiency vs. load current, v out = 2.5 v 13169-012 shutdown current (na) v in (v) 0 20 40 60 80 100 120 140 160 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 ?40oc +25oc +85oc +125oc figure 12 . shutdown current vs. v in , en = l ow 13169-013 efficiency (%) load current (ma) 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 v in = 3.0v v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v v in = 2.5v figure 13 . pwm efficiency vs. load current, v out = 1.8 v 13169-014 efficiency (%) load current (ma) 0 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 v in = 3.6v v in = 4.2v v in = 5.0v v in = 6.0v figure 14 . pwm efficiency vs. load current, v out = 3.3 v 13169-015 quiescent current (na) v in (v) 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 ?40oc +25oc +85oc +125oc 100 150 200 250 300 350 figure 15 . hysteresis quiescent current vs. v in , sync/mode = l ow
ADP5301 data sheet rev. a | page 10 of 21 13169-016 feedback voltage (mv) temperature (c) 797 798 799 800 801 ?40 +25 +85 +125 figure 16 . feedback voltage vs. temperature, pwm mode 13169-017 high-side r ds (on) h (m) v in (v) 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 100 200 300 400 500 600 700 ?40oc +25oc +125oc figure 17 . high - side r ds (on) h vs. v in 13169-018 peak current limit (ma) temperature (c) ?40 +25 +85 +125 840 890 940 990 1040 1090 figure 18 . peak current limit vs. temperature 13169-019 feedback voltage (mv) temperature (c) ?40 +25 +85 +125 792 794 796 798 800 802 804 806 808 810 active to standby standby to active figure 19 . feedback voltage vs. temperature , hysteresis mode 13169-020 low-side r ds (on) l (m) v in (v) 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 ?40oc +25oc +125oc 100 150 200 250 300 350 400 figure 20 . low - side r ds (on) l vs. v in 13169-021 peak current limit (ma) v in (v) 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 800 850 900 950 1000 1050 1100 1150 1200 ?40oc +25oc +125oc figure 21 . peak current limit vs. v in
data sheet ADP5301 rev. a | page 11 of 21 13169-022 uvlo threshold (v) temperature (c) ?40 +25 +85 +125 1.96 1.98 2.00 2.02 2.04 2.06 2.08 2.10 rising falling figure 22 . uvlo threshold, rising and falling vs. temperature ch4 140m a 4 1 2 13169-023 ch2 2.00v ch4 500m a ch1 100mv m 200 s a t 39.60% v out i l sw figure 23 . steady waveform of hysteresis mode, i load = 1 ma (i l is the inductor current) ch1 1.22v 2 1 3 4 13169-024 ch2 5.00v ch4 500m a ch1 1.00v m 200 s a t 50.60% b w ch3 2.00v b w b w v in v out i l sw figure 24 . soft start, i load = 300 ma 13169-025 switching frequency (khz) v in (v) 2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5 1.7 1.8 1.9 2.0 2.1 2.2 2.3 ?40oc +25oc +125oc figure 25 . switching frequency vs. v in ch2 2.72v 2 1 4 13169-026 ch2 2.00v ch4 200m a ch1 10.0mv m 400 ns a t 90.60% b w b w v out (ac) i l sw figure 26 . steady waveform of pwm mode, i load = 300 ma 2 1 4 13169-027 v out v in i l sw ch1 1.05v ch2 5.00v ch4 500m a ch1 500mv m 100 s a t 40.00% b w ch3 2.00v b w b w figure 27 . s oft start with p recharge function
ADP5301 data sheet rev. a | page 12 of 21 1 4 13169-028 v out (ac) i out ch4 11 1m a ch4 50.0m a ch1 50.0mv m 200 s a t 20.80% b w b w figure 28 . load transient of hysteresis mode, i load from 0 ma to 50 ma 1 2 4 13169-029 v out (ac) v in i l sw ch3 4.72v ch2 5.00v ch4 500m a ch1 50.0mv m 2.00 ms a t 30.00% b w b w ch3 2.00v b w figure 29 . line transient of hysteresis mode, i load = 1 0 a , v in from 2.5 v to 6 v 1 4 13169-030 v out v in i l ch3 4.80v ch4 200m a ch1 1.00v m 10.0 ms a t 40.20% b w b w ch3 1.00v b w figure 30 . input v oltage r amp u p and ramp d own in hysteresis mode 1 4 13169-031 v out (ac) i out ch4 308m a ch4 200m a ch1 50.0mv m 200 s a t 20.40% b w b w figure 31 . load transient of pwm mode, i load from 125 ma to 375 ma 1 2 3 4 13169-032 v out (ac) v in i l sw ch3 4.28v ch2 5.00v ch4 500m a ch1 10.0mv m 2.00 m s a t 30.20% b w b w ch3 2.00v b w figure 32 . line transient of pwm mode, i load = 5 00 ma , v in from 2.5 v to 6 v 1 3 2 13169-033 v out v outok sw ch1 1.32v ch2 2.00v ch1 1.00v m 200 s a t 40.00% b w b w ch3 1.00v b w figure 33 . voutok function
data sheet ADP5301 rev. a | page 13 of 21 1 4 2 13169-034 v out i l sw ch1 1.44v ch2 2.00v ch1 2.00v m 10.0 s a t 40.20% b w ch4 500m a figure 34 . output s hort protection 13169-035 sync/ mode sw ch2 1.40v ch2 2.00v ch1 2.00v m 400 n s a t 50.00% b w 1 2 figure 35 . synchronized to 2.5 mhz 13169-036 v out i l sw ch1 1.44v ch2 2.00v ch1 2.00v m 1.00 ms a t 40.20% b w ch4 500m a 4 1 2 figure 36 . output short recovery 3 1 2 13169-037 en v out sw ch3 1.64v ch2 2.00v ch1 1.00v m 4.00 ms a t 40.00% b w b w ch3 2.00v b w figure 37 . quick output discharge function
ADP5301 data sheet rev. a | page 14 of 21 theory of operation th e ADP5301 is a high efficien cy, ultra low quiescent current step - down regulator in a 9 - ball wlcsp to meet demanding performance and board space requirements. the device enables direct connection to the wide input voltage range of 2. 1 5 v to 6. 5 0 v , allowing the use of multiple a lkaline/nimh or li - ion cells and other power sources. buck regulator operation modes pwm mode in pwm mode, the buck regulator in the ADP5301 o perate s at a fixed fr equency that is set by an internal oscilla tor. at the start of each oscillator cycle, the high - side mosfet switch turns on and send s a positive voltage across the inductor. the inductor current increases until the current sense signal exceeds the peak indu ctor current threshold , which turns off the high - side mosfet switch . t his threshold is set by the error amplifier output. during the high - side mosfet off time, the inductor current decreases through the low - side mosfet until the next oscillator clock pulse starts a new cycle. hysteresis mode in h ysteresis mode, the buck regulator in the ADP5301 charges the output voltage slightly higher than its nominal output voltage with pwm pulses by regulating the constant peak inductor current . when t he output voltage increases until the output sense signal exceeds the hysteresis upper threshold, the regulato r enters standby mode. in standby mode, the high - side and low - sid e mosfet s and a majority of the circuitry are disabled to allow a low quiescent current as well as high efficiency performance. during standby mode, the output capacitor supplies energy into t he load and the output voltage decreases until it falls below the hysteresis comparator lower threshold. the buck regulator wakes up and generates the pwm pulses to charge the output again. because the output voltage occasionally enters standby mode and t hen recovers, the output voltage ripple in hysteresis mode is larger than the ripple in pwm mode . m ode selection t he ADP5301 includes the sync /mode pin to allow flexible configuration in h yster esis mode or pwm mode. when a logic high level is applied to the sync/mode pin, the buck regulator is forced to operate in pwm mode . in pwm mode , the regulator can supply up to 500 ma of output current. the regulator can provide lower output ripple and output noise in pwm mode , which is useful for noise sensitive applications . when a logic low level is applied to the sync/mode pin, the buck regulator is forced to operate in h ysteresis mode. in h ysteresis mode , the regulator draws only 18 0 na of quiescent current typic al to regulate the output under zero load , which allows the regulato r to act as a keep - alive power supply in a battery - powered system. in hysteresis mode, t he regulator supplies up to 50 ma of output cur - rent with a relative ly large output ripple compared to pwm mode. the user can alternate between h ysteresis mode and pwm mode during operation. the flexible configuration capability during operation of the device enables efficient power management to meet high efficiency and low output ripple requirements when the system switches between active mode and standby mode. o scillator and synchronization the ADP5301 operates at a 2 mhz switching frequency typical in pwm operat ion mode. the switching frequency of the ADP5301 can be synchronized to an external clock with a frequency range from 1 .2 mhz to 2.5 mhz. the ADP5301 automatically detects the presence of an external clock applied to the sync/mode pin, and the switching frequency transitions to the frequency of the external clock. when the external clock signal stops, the device automatically switches back to the internal clock. adjustable and fixed output voltages the ADP5301 provides adjustable output voltage setting s by connecting one resistor through the vid pin to agnd . the vid detection circuitry works in the start - up period, and t he voltage id code is sampled and held into the internal register and does not change until the next power recycle. furthermore, the adp530 1 provides a fixed output voltage programmed via the factory fuse. in this condition, connect the vid pin to the pvin pin . for t he output volt age settings, the feedback resistor divider is built into the ADP5301 , and the feedback pin (fb) must be tied directly to the output. a n ultralow power voltage reference and an integrated high impedance ( 50 m typical ) feedback divider network contribute to the low quies cent current . table 5 lists the output voltage options by the vid pin configurations . table 5 . output voltage (v out ) options using the vid p in vid configuration v out (v) factory option 0 factory option 1 short to ground 3.0 3.1 short to pvin 2.5 1.3 r vid = 499 k ? 3.6 5.0 r vid = 316 k ? 3.3 4.5 r vid = 226 k ? 2.9 4.2 r vid = 174 k ? 2.8 3.9 r vid = 127 k ? 2.7 3.4 r vid = 97.6 k ? 2.6 3.2 r vid = 76.8 k ? 2.4 1.9 r vid = 56.2 k ? 2.3 1.7 r vid = 43 k ? 2.2 1.6 r vid = 32.4 k ? 2.1 1.4 r vid = 25.5 k ? 2.0 1.1 r vid = 19.6 k ? 1.8 1.0 r vid = 15 k ? 1.5 0.9 r vid = 1 1.8 k ? 1.2 0.8
data sheet ADP5301 rev. a | page 15 of 21 undervoltage lockout (uvlo) the u nderv oltage l ockout c ircuitry monitor s the input voltage level o n the pvin pin . if input voltage falls below 2.00 v (typical) , the regulator turn s off. after the input voltage rises above 2.0 6 v (typical), the soft start period is initiated, and the regulator is enabled when the en pin is high. e nable /d isable the ADP5301 includes a separate enable pin (en) . a l ogic high in the en pin start s the regulator. due to the low quiescent current design, it is typical for the regulato r to start switching after a delay of a few millisecond s from the en pin being pulled h igh . a l ogic l ow o n the en pin immediately disable s the regulator and bring s the regulator into extremely low current consumption . c urrent l imit the buck regulator in the ADP5301 ha s protection circuitry that limit s the direction and the amount of current to a certain level that flows through the high - side mosfet and the low - side mosfet in cycle - by - cycle mode . the positive current limit on the high - side mosfet limits the amount of current that can flow from the input to the output. the negative current limit on the low - side mosfet prevents the inductor current from reversing direction and flowing out of t he load. s hort - c ircuit p rotection the buck regulator in ADP5301 include s frequency foldback to prevent current runaway on a hard short. when the output voltage at the fb pin falls below 0.3 v ty pical , indicating the possibility of a hard short at the output, the switching frequency (in pwm mode) is reduced to one - fourth of the internal oscillator frequency. the reduction in the switching frequency allows more ti me for the inductor to discharge, preventing a runaway of output current. s oft s tart the ADP5301 has an internal soft start function that ramps up the output voltage in a controlled manner upon startup, thereby limiting the inrush current. this feature prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the devic e. t he default t ypical soft start t ime is 350 s for the regulator . a d ifferent soft start time (2800 s) can be programmed for ADP5301 by the factory fuse. startup with a precharged output the buck regulator in the ADP5301 include s a precharged start - up feature to protect the low - side mos fet from damage during startup. if the output voltage is precharged before the regulator turn s on, the regulator prevents reverse inductor current which discharges the output capacitor until the internal soft start reference voltage exceeds the precharged voltage on the feedback pin. 100% d uty cycle o peration when the input voltage approaches the output voltage, the ADP5301 stops switching and enters 100% duty cycle operation . it connects the output via the inductor and the internal high - side power switch to the input. when the input voltage is charged again and the required duty cycle falls to 95% typical, the buck immediately restarts switching and regulation without allowing overshoot on the output voltage. in hysteresis mode , the ADP5301 draws an ul tralow quiescent current of only 570 na typical during 100% duty cycle operation a ctive d ischarge the ADP5301 integrates an optional, factory programmable discharge switch from the switching node to ground. this switch turn s on when its associated regulator is disabled, which helps discharge the output capacitor quickly. the typical value of the discharge switch is 290 ? for the regulator . by default, the discharge function is not enabled. the active discharge function can be enabled by the factory fuse. voutok function the ADP5301 includes an open - drain power - good output ( voutok pin ) that is active high when the buck regulator is operating normally. by default, the voutok pin monitors the output voltage. a logic high on the voutok pin indicates that the regulated output voltage o f the buck regulator is above 9 0 % (typical) of its nominal outpu t. when the regulated output volta ge of the buck regulator falls below 8 7 % (typical) of its nominal outpu t for a delay time greater than approximately 10 s , the voutok pin goes low. thermal shutdown if the ADP5301 junction temperature exceeds 1 42 c, the thermal shutdown circuit turns off the ic except for the internal linear regulator. extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. a 15 c hysteresis is included so that the ADP5301 do es not return to oper ation after thermal shutdown until the junction temper a ture falls below 1 27 c. when the device exits thermal shutdown, a soft start is initiated for the buck regulator .
ADP5301 data sheet rev. a | page 16 of 21 applications information this section describes the external components selection for the ADP5301 . a typical application circuit is shown in figure 38. 13169-038 2.2h sw pgnd fb 10f mlcc 10f mlcc v out = 1.8v pvin sync/ mode en vid v in = 2.15v to 6.50v ADP5301 (9-ball wlcsp) r vid 20k? voutok agnd r1 1m ? figure 38. typical application circuit external component selection the ADP5301 is optimized for operation with a 2.2 h inductor and 10 f output capacitors for various output voltages using the closed-loop compensation and adaptive slope compensation circuits. the selection of components depends on the efficiency, the load current transient, and other application requirements. the trade-offs among performance parameters, such as efficiency and transient response, are made by varying the choice of external components. selecting the inductor the high switching frequency of the ADP5301 allows the use of small surface-mount power inductors. the dc resistance (dcr) value of the selected inductor affects efficiency. in addition, it is recommended to select a multil ayer inductor rather than a magnetic iron inductor because the high switching frequency increases the core temperature rise and enlarges the core loss. a minimum requirement of the dc current rating of the inductor is for it to be equal to the maximum load current plus half of the inductor current ripple (i l ), as shown by the following equations: ? ? ? ? ? ? ? ? ? ? ? ? ? ??? sw in out out l fl v v vi C1 ? ? ? ? ? ? ? ? ? 2 )( l max load pk i ii use the inductor series from different vendors shown in table 6. output capacitor output capacitance is required to minimize the voltage overshoot, the voltage undershoot, and the ripple voltage present on the output. capacitors with low equivalent series resistance (esr) values produce the lowest output ripple. furthermore, use capacitors such as x5r and x7r dielectric capacitors. do not use y5v and z5u capacitors, which are unsuitable choices due to their large capacitance variation over temperature and their dc bias voltage changes. because esr is important, select the capacitor using the following equation: l ripple cout i v esr ? where: esr cout is the esr of the chosen capacitor. v ripple is the peak-to-peak output voltage ripple. increasing the output capacitor value has no effect on stability and may reduce output ripple and enhance load transient response. when choosing the output capacitor value, it is important to account for the loss of capacitance due to output voltage dc bias. use the capacitor series from different vendors shown in table 7. table 6. recommended inductors vendor model inductance (h) dimensions (mm) dcr (m) i sat 1 (a) tdk mlp2016v2r2mt0s1 2.2 2.0 1.6 0.85 280 1.0 wurth 74479889222 2.2 2.5 2.0 1.2 250 1.7 coilcraft lps3314-222mr 2.2 3.3 3.3 1.3 100 1.5 1 i sat is the dc current at which the inductance drops 30% (typical) from its value without current. table 7. input and output capacitors vendor model capacitance (f) size murata grm188d71a106ma73 10 0603 murata grm21br71a106ke51 10 0805 murata grm31cr71a106ka01 10 1206
data sheet ADP5301 rev. a | page 17 of 21 input capacitor an input capacitor is required to reduce the input voltage ripple, input ripple current, and source impedance. place the input capacitor as close as possible to the p vin pin. a low esr x7r or x5r capacitor is highly recommended to minimize the input voltage ripple. use the following equation to determine the rms input current: in out in out max load rms v v v v i i ) ( ) ( ? efficiency efficiency is the ratio of output power to input power. the high efficien cy of the ADP5301 has two distinct advantages. first, only a small amount of power is lost in the dc - to - dc c onverter package , which in turn reduces thermal constraints. second, the high efficiency delivers the maximum output power for the given input power, thereby extending battery life in portable applications. power switch conduction losses power switch dc conduction losses are caused by the flow of output current through the high - side p - channel power switch and the low - side n - channel synchronous rectifier, which have internal resistances (r ds (on) ) associated with them. the amount of power loss is approximated by p sw_cond = ( r ds (on) h d + r ds (on) l (1 ? d )) i out 2 where : in out v v d = inductor losses inductor conduction losses are caused by the flow of current through the inductor, which has an internal dcr associated with it. larger size inductors have smaller dcr, which can decrease inductor conduction losses. inductor core losses relate to the magnetic permeability of the core material . because the ADP5301 is a high switching frequency dc - to - dc regulator , shielded ferrite core material is recommended because of its low core losses and low electromagnetic interference ( emi ) . to estimate the total amount of power lost in the inductor, use the following equation: p l = dcr i out 2 + core losses driver losses driver losses are associated with the current drawn by the driver to t urn on and turn off the power devices at the switching freque ncy. each time a power device gate is turned on and turned off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. e stimate driver losses using the following equation: p driver = ( c gate_ h + c gate_ l ) v in 2 f sw w here: c gate_ h is the gate capacitance of the internal high - side switch. c gate_ l is the gate capacitance of the internal low - side switch. f sw is the switching frequency in pwm mode . the typical value s for the gate capacitances are 69 pf for c gate_h and 31 pf for c gate_l . transition losses transition losses occur because the p - channel switch cannot turn on or turn off instantaneously. in the middle of a s witch node transition, the power switch provides all of the inductor current. the source to drain vol tage of the power switch is half of the input voltage, resulting in power loss. transition losses increase with both load current and input voltage and occur twice for each switching cycle. use the following equation to estimate transition losses: p tran = v in /2 i out ( t r + t f ) f sw where: t r is the rise time of the sw node. t f is the fall time of the sw node. the typical value for the rise and fall times, t r and t f , is 2 ns.
ADP5301 data sheet rev. a | page 18 of 21 printed circuit board (pcb ) layout recommendations 13169-039 en pgnd pvin agnd gnd sync/ mode vid fb sw ADP5301 vin 3.00 3.60 vout 10f 10v/xr5 0603 10f 6.3v/xr5 0603 voutok l1 ? 2.2h 0603 100k ? 0201 b1 b2 b3 a1 a2 a3 c1 c2 c3 figure 39. typical pcb layout
data sheet ADP5301 rev. a | page 19 of 21 typical application circuits the ADP5301 can be used as a keep-alive, ultralow step-down power regulator to extend the battery life (see figure 40) and as a battery- powered equipment or wireless sensor network controlled by a microcontroller or a processor (see figure 41). 13169-040 2.2h sw pgnd fb 10f 10f v out = 1.8v pvin vid en li-ion batter y sync/mode v in = 3.0v to 4.2v ADP5301 r vid 20k ? 1% voutok agnd figure 40. typical ADP5301 application with li-ion battery 13169-041 2.2h sw pgnd fb 10f r1 1m ? 10f v out = 1.8v adc/rf/afe mcu (always on) pvin vid en sync/mode v in = 2.0v to 3.0v ADP5301 r vid 20k ? 1% voutok agnd two alkaline or nimh batteries figure 41. typical ADP5301 application with two alkaline/nimh batteries
ADP5301 data sheet rev. a | page 20 of 21 factory programmable options to order a device with options other than the default options, contact your local analog devices sales or distribution representative . table 8 . output voltage vid setting options option description option 0 vid r esistor to set the output voltage as: 1.2 v, 1.5 v, 1.8 v, 2.0 v, 2.1 v, 2.2 v, 2.3 v, 2.4 v, 2.5 v, 2 .6 v, 2.7 v, 2.8 v, 2.9 v, 3.0 v, 3.3 v, or 3. 6 v (default) option 1 vid r esistor to set the output voltage as: 0.8 v, 0.9 v, 1.0 v, 1.1 v, 1.3 v, 1.4 v, 1.6 v, 1.7 v, 1.9 v, 3.1 v, 3.4 v, 3.9 v, 4.2 v, 4.5 v, or 5.0 v table 9 . output discharge functionality options option description option 0 output discharge function disabled for buck regulator (default) option 1 output discharge funct ion enabled for buck regulator table 10. soft s ta rt time options option description option 0 350 s (default) option 1 28 00 s
data sheet ADP5301 rev. a | page 21 of 21 outline d imensions 05-20-2014- a a b c 0.660 0.600 0.540 1.690 1.650 1.610 1.910 1.870 1.830 1 2 3 bot t om view (bal l side up) t op view (bal l side down) end view 0.360 0.320 0.280 1.00 ref 0.50 bsc sea ting plane 0.270 0.240 0.210 0.345 0.325 0.305 0.455 0.435 0.415 0.390 0.360 0.330 coplanarity 0.04 bal l a1 identifier pkg-003773 figure 42 . 9- ball wafer level chip scale package [wlcsp] (cb - 9 - 6) dimensions shown in millimeters ordering guide model 1 t emperature range package description package option ADP5301acbz - 1 - r7 ?40c to +125c 9 - ball wlcsp , output voltage option 0 w ith output discharge cb -9 -6 adp530 1 acbz - 2 - r7 ?40c to +125c 9 - ball wlcsp , output voltage option 0 without output discharge cb -9 -6 ADP5301acbz - 3 - r7 ?40c to +125c 9 - ball wlcsp, output voltage option 1 w ith output discharge cb -9 -6 ADP5301 - evalz evaluation board 1 z = rohs compliant part. ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d13169 - 0 - 12/15(a)

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